`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:16:48 02/26/2009 
// Design Name: 
// Module Name:    regalu 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module regalu(Aselect,Bselect,Dselect,abus,bbus,dbus,clk,S,shamt,Cin,signext,imm,mem_dbus,eq_det_out,Cout);
parameter N=32;

input clk,Cin,imm;

input [N-1:0] Aselect,Bselect,Dselect,signext,mem_dbus;

output [N-1:0] abus,bbus,dbus;

input [3:0] S;
input [4:0]shamt;
output eq_det_out,Cout;


wire[31:0] wiremux0,pipedbbus,wireabus,pipedabus;



regfile RF(
	
.Aselect(Aselect),
	
.Bselect(Bselect),
	
.Dselect(Dselect),
	
.clk(clk),
	
.abus(wireabus),
	
.bbus(wiremux0),
	
.dbus(mem_dbus)

);

equality_det equal_detector(
	.in1(wireabus),
	.in2(wiremux0),
	.clk(clk),
	.out(eq_det_out)
	);




alupipe A(
	
.abus(wireabus),
	
.bbus(wiremux0),
	
.dbus(dbus),
	
.clk(clk),
	
.S(S),
	
.Cin(Cin),
.imm2(imm),
.signext(signext),
.pipedbbus(pipedbbus),
.pipedabus(pipedabus),
.Cout(Cout),
.shamt(shamt)

);

assign bbus=wiremux0;
assign abus=wireabus; //the line I changed from pipedabus to wireabus




endmodule
